Hello,
I was using the CC1120 transceiver in serial synchronous mode. I wanted to check the sensitivity of CC1120 in serial synchronous mode. I transmitted data consisting of 1s and 0s from the signal generator, fed it to the CC1120 using a RF cable.There is a micro-controller as the interface between CC1120 and computer.The microcontroller receives data from CC1120 and sends it to the computer. It was observed that the least output power from signal generator at which CC1120 could receive the data was around -80 dBm. Whereas when the CC1120 was used in packet mode, this power was around -115 dBm.
At the same time, when a low noise amplifier (LNA) was used at the receiver side of CC1120 it was observed that, the least power on signal generator for data to be received on CC1120 was around -120dbm in serial synchronous mode.The gain of the LNA was around 40 dB.When the LNA was used in packet mode, the least power observed was around -120 dBm.
So my doubts are, is it that the sensitivity of CC1120 in serial synchronous mode around -80 dBm ? If so why is it so low ?
The settings of the CC1120 for serial synchronous mode were as follows:Am I missing something or is anything wrong ?
Code:
txrWriteReg(DRATE2, 0x73); //DRATE 9600
txrWriteReg(DRATE1, 0xA9);
txrWriteReg(DRATE0, 0x2A);
txrWriteReg(IOCFG3, 0xB0); //GPIO3 IO Pin Configuration
txrWriteReg(IOCFG2, 0x08); //GPIO2 IO Pin Configuration
txrWriteReg(IOCFG1, 0xB0); //GPIO1 IO Pin Configuration
txrWriteReg(IOCFG0, 0x09); //GPIO0 IO Pin Configuration
txrWriteReg(SYNC_CFG1, 0x0B); //Sync Word Detection Configuration Reg. 1Sync Word Disabled
txrWriteReg(SYNC_CFG0, 0x00); //---Sync Word Detection Configuration Reg. 0Sync Disabled
txrWriteReg(DEVIATION_M, 0xB0); //Frequency Deviation Configuration
txrWriteReg(MODCFG_DEV_E, 0x02); //000Modulation Format and Frequency Deviation Configur.. 3.3 khz
txrWriteReg(DCFILT_CFG, 0x1C); //Digital DC Removal Configuration
txrWriteReg(PREAMBLE_CFG1, 0x1B);
txrWriteReg(PREAMBLE_CFG0, 0x0A);//---For no preamble
txrWriteReg(IQIC, 0xC6); //Digital Image Channel Compensation Configuration XXX initial value
txrWriteReg(CHAN_BW, 0x08); //Channel Filter Configuration
txrWriteReg(MDMCFG0, 0x01); //000General Modem Parameter Configuration Reg. 0 in serial code used
txrWriteReg(MDMCFG1, 0x86) ;//--- testing TO IMPLEMENT THRESHOLD
txrWriteReg(AGC_REF, 0x20); //AGC Reference Level Configuration
txrWriteReg(AGC_CS_THR, 0xAF); //000Carrier Sense Threshold Configuration For testingAB=-85 9E=-100 A4=-95
txrWriteReg(AGC_CFG1, 0x09); //Automatic Gain Control Configuration Reg. 1 agc integration window size
txrWriteReg(AGC_CFG0, 0xC3); //Automatic Gain Control Configuration Reg. 0 check rssi after 2 samples
txrWriteReg(FIFO_CFG, 0x00); //FIFO Configuration
txrWriteReg(SETTLING_CFG, 0x03); //Frequency Synthesizer Calibration and Settling Con..
txrWriteReg(FS_CFG, 0x14); //Frequency Synthesizer Configuration
txrWriteReg(PKT_CFG0, 0x40); //000Packet Configuration Reg. 0
txrWriteReg(PKT_CFG1, 0x00); //Packet Configuration Reg. 1
txrWriteReg(PKT_CFG2, 0x01);// Enable synchronous serial mode
txrWriteReg(IF_MIX_CFG, 0x00); //IF Mix Configuration
txrWriteReg(FREQOFF_CFG, 0x22); //Frequency Offset Correction Configuration
txrWriteReg(FREQ2, 0x6d); //Frequency Configuration [23:16]
txrWriteReg(FREQ1, 0x41); //Frequency Configuration [15:8]
txrWriteReg(FREQ0, 0xd2); //Frequency Configuration [7:0] - Board A
txrWriteReg(FS_DIG1, 0x00); //Frequency Synthesizer Digital Reg. 1
txrWriteReg(FS_DIG0, 0x5F); //Frequency Synthesizer Digital Reg. 0
txrWriteReg(FS_CAL1, 0x40); //Frequency Synthesizer Calibration Reg. 1
txrWriteReg(FS_CAL0, 0x0E); //Frequency Synthesizer Calibration Reg. 0
txrWriteReg(FS_DIVTWO, 0x03); //Frequency Synthesizer Divide by 2
txrWriteReg(FS_DSM0, 0x33); //FS Digital Synthesizer Module Configuration Reg. 0
txrWriteReg(FS_DSM1, 0x02); //FS Digital Synthesizer Module Configuration Reg. 0 added new
txrWriteReg(FS_DVC0, 0x13); //Frequency Synthesizer Divider Chain Configuration ..
txrWriteReg(FS_DVC1, 0xf3); //Frequency Synthesizer Divider Chain Configuration .. added new
txrWriteReg(FS_PFD, 0x50); //Frequency Synthesizer Phase Frequency Detector Con..
txrWriteReg(FS_PRE, 0x6E); //Frequency Synthesizer Prescaler Configuration
txrWriteReg(FS_REG_DIV_CML, 0x14); //Frequency Synthesizer Divider Regulator Configurat..
txrWriteReg(FS_SPARE, 0xAC); //Frequency Synthesizer Spare
txrWriteReg(FS_VCO0, 0xB3); //FS Voltage Controlled Oscillator Configuration Reg.. testing
txrWriteReg(XOSC5, 0x0E); //Crystal Oscillator Configuration Reg. 5
txrWriteReg(XOSC1, 0x03); //Crystal Oscillator Configuration Reg. 1 testing
txrWriteReg(AGC_GAIN_ADJUST, 0x9E); // RSSI Offset
txrWriteReg(PA_CFG2, 0x3F);